With the ever-increasing circuit density in integrated circuits, demands on the multilevel metallurgy necessary to connect the individual circuits in the integrated circuit have been more demanding. Because of space limitations, particularly in lateral dimensions, there have been requirements that the via holes through the insulative layers separating different layers of metallurgy have smaller and smaller lateral dimensions relative to the vertical dimensions of such holes. Of course, the vertical dimensions of such via holes remain limited by the thickness of the insulative layer which is required to thoroughly electrically insulate one level of metallurgy from another. We have found, that with insulative layers having thicknesses of two microns or greater and with metallurgies deposited on such insulative layers which are thinner than the insulative layer, there is a problem of discontinuity of the metal deposited in the via holes.
In order to illustrate this prior art problem, reference is made to FIGS. 1A and 1B of the drawings. In such a typical prior art structure substrate 10 has formed thereon an insulative layer 11 which serves to insulate the substrate from the first layer of metallurgy or the first level metallurgical pattern 12. Conventional contact openings, which need not be shown for purposes of illustrating the present invention, extend through insulative layer 11 connecting various active regions, i.e., N- or P-type regions, formed in the semiconductor or silicon substrate 10 to the first level of metallurgy 12. A second layer of insulative material 13 covers metallurgy layer 12 and insulates metallurgy layer 12 from a second level of metallurgy which will be formed on the surface of insulative layer 13. In order to interconnect metallurgy layer 12 to this second level of metallurgy, it is necessary to have via holes 14 which are selectively positioned to interconnect metallurgy layer 12 with the upper layer of metallurgy. Conventionally, it has been the practice to deposit the second layer of metallurgy 15 as a blanket deposition in a single step so that layer 15 will, as shown in FIG. 1B, deposit on the surface of insulative layer 13 as well as in via holes 14. With relatively deep via holes such as those required to penetrate through insulative layers such as layer 13 having thicknesses in the order of two microns, if the metallurgy being deposited in the blanket deposition has a thickness of less than two microns, e.g., conventional integrated circuit metallurgies have thicknesses in the order of from 1 to 1.3 microns, discontinuities such as discontinuities 16 shown in FIG. 1B tend to occur interfering with the continuity of the conductive path from the metal in the via hole to the remainder of the metallization pattern which is subsequently formed from blanket metal layer 15 in the conventional manner.